In this project, we are very active on the logic style analysis with a strong emphasis on low-power unipolar logic gates. We have been able to reduce the inherently present static leakage current of inverters. The result of this route has been recently published as crossover logic, yielding a fivefold reduction in power consumption. Besides this novel circuit architecture, we have improved the power consumption of regular circuit topologies necessary to enable capacitive readout circuits. The aforementioned circuit consumed less than 160nW.
Introducing the Moore’s law on flex roadmap, we have pursuing downscaling until 1.5µm. The target in this ERC project is to move towards VLSI circuits on flex, which required a stable downscaled transistor. As a result, the 1.5µm transistors embedded in a ring oscillator yielded the fastest reported metal-oxide based circuit exhibiting a stage delay of only 2.4ns on flexible substrates.
One of the routes in this project is to innovate at system level design, enabling new applications for this technology. The first real application that was realized is the world-first IGZO-based NFC tag due to a few key achievements within this project: (1) downscaling of the self-aligned technology yielding NFC-compatible operating voltages and inverter delays enabling direct clock recovery; (2) introducing low-power design technique like logic style partitioning and optimization for speed, robustness and low power. The NFC tag was well-received by the TFT community, leading to an ISSCC paper, an invited perspective article in Nature Electronics and several invited talks at conferences.
The second application window that was envisioned are healthcare patches and sensor-node IoT devices. In this field, the team has worked on analog-to-digital converters as key circuit blocks for such systems, which are published in several papers.
A third crucial item for flexible electronic systems is memory, both non-volatile and volatile. We have demonstrated an 8kb laser programmable memory and the first readout of non-volatile memory cells.
Security will be a key topic for edge computing and patches. A cryptographic chip is implemented with a large number of transistors. Therefore, we have selected a cryptochip which executes a lightweight algorithm and realized the world-first security chip on flex. This was well received at the CHES conference in 2019 and won the best paper award.